The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to an erasable (by use of ultraviolet rays) programmable read-only memory (EPROM) having two transistors with a common floating gate and two separate drains, one of which serves as a read drain and the other of which serves as a write drain.
FIG. 1 shows part of a conventional EPROM having cell transistors. Bit line 62 is connected to the drain (D) of cell transistor 61. Word line 63 is connected to the control gate (G) of transistor 61. A ground voltage circuit is connected to the source (S) of transistor 61. Bit line 62 is commonly used in the read and write modes. Since the read time is longer than the write time, unintentional writing could occur by injection of hot electrons generated in the read mode. In order to prevent this drawback, bit line clamp circuit 64 is connected to bit line 62, and a bit line voltage (i.e., the drain voltage of transistor 61) is clamped to a level (e.g., 1 to 2 V) considerably lower than the power source voltage.
When the bit line voltage is kept at a very low level, the magnitude of the memory cell current becomes insufficient, and the electrostatic capacitance of bit ine 62 increases drastically. The slewing rate of the bit line voltage then becomes undesirably lower than that of other memory devices such as a static random-access memory (SRAM).